Conventionally, a flash memory has been used as a nonvolatile memory.
In this flash memory, as shown in FIG. 28, a memory cell is constituted such that a semiconductor substrate 901 includes thereon, via a gate insulating film, a floating gate 902, an insulating film 907, and a word line (control gate) 903 in this order, and a source line 904 and a bit line 905 are formed on both sides of the floating gate 902. Around the memory cell, an element separation region 906 is formed (for example, Japanese Laid-Open Patent Application No. 304277/1993 (Tokukaihei 5-304277; published on Nov. 16, 1993).
The memory cell holds memory depending upon the amount of charges in the floating gate 902. A memory cell array which is an array of memory cells enables rewriting and read-out operations with respect to intended memory cells by applying a predetermined voltage to particularly selected word lines and bit lines.
Such a flash memory shows drain current (Id) to gate voltage (Vg) characteristics as shown in FIG. 29 with variation in the amount of charges in the floating gate. Increase in the amount of negative charges in the floating gate increases a threshold value, and an Id-Vg curve moves substantially parallel to the direction where Vg increases.
However, such a flash memory has the following problems: it is functionally necessary that the insulating film 907 is placed to isolate the floating gate 902 from the word line 903; and it is difficult to reduce the thickness of the gate insulating film to prevent leakage of charges from the floating gate 902. Therefore, it is difficult to realize the reduction in thickness of the insulating film 907 and the gate insulating film, interfering with the realization of a finer memory cell.